1. Field of the Invention
The present invention relates to a semiconductor device and a method for production thereof. More particularly, the present invention relates to a semiconductor device of field-effect transistor structure and a method for production thereof, the semiconductor device having improved carrier mobility that results from stress applied to the channel part in the semiconductor substrate.
2. Description of the Related Art
Integrated circuits with field-effect transistors are becoming miniaturized continuously in pursuit of such advantages as higher speed, less power consumption, lower production cost, and smaller size. Now, the miniaturization has reached the stage where it is technically possible to produce transistors having the gate length shorter than 100 nm. Moreover, the roadmap of ITRS (International Technology Roadmap for Semiconductors) envisages that the transistor called 32 nm node will have a gate length shorter than 20 nm.
The reduction of gate length is also accompanied by the downsizing (scaling) of the device structure itself. However, reducing the gate length from the order of submicron to the order of 100 nm or less is impeded by the physical thickness of the silicon oxide (SiO2) insulating film, which is conventionally used as the gate insulating film, from the standpoint of suppressing gate leak current.
Possible ways under study to reduce the effective thickness of the gate insulating film are by making the gate insulating film from hafnium oxide, which has a high dielectric constant (high-K), thereby raising the dielectric constant of the gate insulating film, or by making the gate insulating film from a metallic material, thereby preventing the gate electrode from depletion.
The method for preventing the gate electrode from depletion is being investigated by making the gate electrode from such metallic materials as tungsten (W), titanium (Ti), hafnium (Hf), ruthenium (Ru), and iridium (Ir). Unfortunately, these metallic materials react with the gate insulating film upon heat treatment at a high temperature, thereby deteriorating the gate insulating film and fluctuating the threshold voltage. This problem is involved in the heat treatment for activation of impurities that is carried out in the process in related art in which the gate electrode is formed and then the impurity diffusion layer, such as source-drain region, is formed.
One way proposed so far to address the problem with the gate electrode of metallic material is the damascene gate process which is intended to form the source-drain region and then form the gate electrode (see Japanese Patent Laid-open Nos. 2000-315789 and 2005-26707). According to the damascene gate process, the source-drain region is formed, with a dummy gate formed previously. Then an interlayer insulating film that covers the dummy gate is formed, and subsequently it is polished so that the dummy gate is exposed. The dummy gate is removed by etching, and in the removed part are formed a new gate insulating film and a gate electrode. This process protects the gate electrode from the effect of heat treatment to activate impurities in the formation of the source-drain region.
On the other hand, there are some techniques which are being actively used to increase the carrier mobility in the channel part by application of stress to the channel part in the silicon substrate.
One of such techniques is composed of forming a trench in the silicon substrate adjacent to the gate electrode having a side wall and forming in the trench by epitaxial growth the source-drain which is a semiconductor layer differing in lattice constant from silicon (Si). The semiconductor layer constituting the source-drain formed in this manner applies stress to the channel part (see Japanese Patent Laid-open No. 2006-186240).
There is another technique proposed so far. It is concerned with a MOS (Metal Oxide Semiconductor) transistor Tr formed on the surface of the substrate 101 as shown in FIG. 11. The transistor Tr has the silicide layer 103 on its source-drain (S/D), and the transistor Tr and the substrate 101 are covered with the stress liner film 105 which applies stress. The stress liner film 105 is that of tensile stress type or compressive stress type depending on whether the MOS transistor (Tr) is that of n-channel type or p-channel type, respectively. This structure permits the silicide layer 103 and the stress liner film 105 to apply stress to the channel part (ch) of the transistor (Tr) (see Japanese Patent Laid-open Nos. 2002-198368, 2005-57301, 2006-165335 and 2006-269768).